Jesse Gillingham

This project focuses on creating a versatile path planning system for unmanned aerial vehicles (UAVs) used in outdoor exploration. The system generates a 3D navigation plan based on detected objectives and wind patterns during flight. The approach involves developing a reinforcement learning (RL) policy in a simulation, training it on real aerial imagery, and deploying it on a quadcopter for real-world target detection.

This project focuses on making a functional website to display my projects, research, and experiments. The website hosts information about me and my projects. Its aim is to display my work and allow other people to constructively criticize and ask questions. This helps me to improve upon my in and to continually grow personally and professionally. The website is written in pure HTML and CSS so it can be easily replicated and modified. I have chosen to host it on Github for its wonderful version control. To progress this project further I am thinking about incorporating Javascript and will continue to refine its design.

The single-cycle CPU design for the MIPS ISA is a straightforward and efficient processor architecture where each instruction is executed within a single clock cycle. This approach simplifies the control logic and allows for predictable and consistent instruction execution times. The CPU fetches instructions from memory, decodes them, performs necessary operations in an arithmetic logic unit (ALU), and stores the results all within one cycle. Key components include instruction memory, a control unit, an ALU, data memory, and registers for temporary data storage.

The pipelined CPU design for the MIPS ISA is a branch off of the single-cycle project. This project, MIPS pipelined CPU, attempts to make massive improvements to the execution time of the CPU. We decided to go with a five stage pipeline with our branch and jump handling unit in the execution stage. This project has no branch prediction and will have to flush pipes to properly execute a branch. We do later implement a forwarding unit and a hazard detection unit to handle program hazards.